1. Field of the Invention
The present invention relates to a set associative cache memory of the type organized in blocks and adapted to provide a high-speed buffer between plural accessing units and a relatively low speed main memory of a CPU. More particularly, the present invention relates to a novel circuit arrangement and error control monitoring circuitry for accessing memory addresses in a high-speed cache memory.
2. Description of the Prior Art
The purpose of a set associative cache memory is to provide a high-speed buffer to serve as a temporary memory between the low speed main memory and requesting unit or units which have access to the processing system. Our aforementioned U.S. Pat. No. 4,168,541 describes what was then called a high-speed set associate cache memory. The cache memory of this prior art patent was designed approximately ten years ago and has been employed in commercially available computers sold by Unisys (formerly Sperry) as models 1100/80 and 1100/90 high-speed computers. The data array cache memory employed in this prior art patent describes a cache memory for storing 512 sets of four words each arranged in four blocks, each representing one-quarter of the cache memory. Each of the four blocks were arranged on a separate circuit board or mother board. The cache memory disclosed in this prior art patent provided a total capacity of 8K full words or 32K quarter words. The full words comprised thirty-six data bits and four parity bits which were composed of one quarter of a full word from each of the four blocks.
The present invention partitions its cache memory in a similar manner but comprises 32K full words of forty bits stored in RAM memory chips. The size of the memory of the present invention is four times that of the prior art cache memory. It is well known that the access time for a unique address in memory increases with the size of the memory. Thus, if the circuit arrangement of the prior art cache memory is linearally expanded, the access time for an address in memory would logically be increased. While it is possible to increase the switching time of the logic gate circuits, it is not possible to decrease the data array access time lower than the 14 to 15 nanoseconds presently required.
Accordingly, there is a current need for a set associative cache memory having larger capacity and faster access times than those provided in the prior art cache memories.